In the design and development of semiconductor devices an important consideration has long been to reduce the operating power required and thereby also reduce related problems of temperature, apparatus size and other factors. With complementary or CMOS semiconductor devices, power is essentially consumed only during a change of state of a gate or cell and thus, power requirements for large CMOS arrays are relatively low as compared with P-channel or N-channel devices. However, in prior CMOS devices, such as large memory arrays, excessive power was consumed and current flow variations occurred during certain functions of the circuit, due to several factors. In the fabrication processing of CMOS devices, inherent processing differences are created between P-channel and N-channel elements of the array. Such process differences or variations may occur due to a number of factors such as: (1) the gate oxide thickness, a critical parameter in the strength of the circuit elements or transistors; (2) electrical W or width of the transistor; (3) the poly-L of the transistor which is the distance between its drain and source as laid out in the circuit; and (4) impurity doping concentration in the channel of the transistor. Heretofore, these process differences caused mismatching between elements that resulted in variations of and excessive current flow through related devices, thereby causing excessive power consumption and sometimes malfunctioning of the circuit.
Another problem with prior CMOS memory devices, particularly those utilizing a single N-channel transistor as a bias means for each bit line or column, was that the bias transistors inherently drew excessive current as they were pulled up to prebias the bit lines of the memory device to a predetermined voltage. The present invention provides a means for eliminating this excessive current flow to thereby decrease the overall power consumption for the memory devices while also compensating for the aforesaid process variation.